As is well known, electronic memory devices of the EPROM or FLASH-EPROM type require that a matrix type of layout be produced on a semiconductor substrate wherein a plurality of bit lines, formed of floating gate regions, are crossed over by a plurality of conductive strips, or word lines.
A known process of manufacturing memory devices of the EPROM or EEPROM type, more particularly EPROM, FLASH EPROM and EEPROM memory devices of the virtual ground, cross-point type, is described in European Patent No. 0 573 728, for example, incorporated herein by reference.
This prior document discloses an integrated device of the EPROM or FLASH EPROM type, wherein individual memory blocks include a matrix of cells comprising a plurality of word lines and a plurality of bit lines, lying orthogonally to each other. The multiple cross-points between the word lines and the bit lines define the memory cells.
A structure of this kind is known in the art as a "tablecloth" or cross-point matrix, and is peculiar in that the bit lines are formed in the semiconductor substrate by parallel, continuous diffused strips.
An advantageous aspect of this particular arrangement resides in the absence of metal contacts from the substrate area which is to accommodate the integrated memory cells; this feature greatly expands the capacity for integration on the semiconductor substrate.
Metal contacts are only formed at the opposite ends of the bit lines, and provide termination pads for each memory block.
For the present invention to be more readily understood, the conventional processing steps involved in defining, on a semiconductor substrate, the matrix layout of a virtual ground EPROM device having bit lines with floating gate regions will be recalled briefly herein below.
Starting with a semiconductor substrate 1, such as that shown in FIG. 1, which has been provided with a pattern of active areas and an optional layer 2 of field separation oxide, multiple depositions are performed over the entire substrate surface.
A thin layer 3 of tunnel oxide is deposited first. Thereafter, a first layer 4 of polysilicon, referred to as the Poly1, is deposited. This is followed by the deposition of a second dielectric layer 5 of the interpoly type, e.g., of ONO, which is then topped with a further deposition of a second layer 6 of polysilicon, the latter being also referred to as the poly cap.
At this stage, a photolithographic step using a mask 16, also referred as the Poly1 mask or 556 mask hereinafter, is carried out to define the layouts of the gate regions and their associated bit lines.
A self-aligned cascade etching step is carried out next to remove parallel strips from multiple layers, down to the active areas of the substrate 1.
This cascade etching operation will remove the poly cap layer 6, ONO layer 5, Poly1 layer 4, tunnel oxide layer 3, and field oxide 2 from the unprotected areas by the 556 mask.
As a result, a spatial geometry is defined on the semiconductor substrate 1 which includes a plurality of parallel lines, e.g., bit lines of memory cells and corresponding gate regions 13.
FIG. 2 is a schematic plan view of the pattern created by the etching step.
The gate regions 13 are formed of the stack or stacked structure of poly cap-ONO-Poly1-tunnel oxide and an optional field oxide, as shown in FIG. 1A.
After completion of the self-aligned etching, the 556 mask is removed and a second mask, referred to as the 585 mask, is formed to allow for a source implantation to be performed, as shown in FIG. 1A.
The 585 mask comprises long strips running parallel to the bit lines and fully covering drain lines 17, shown in FIG. 2, and in part the poly cap layer 6 as well.
Subsequent implantations are performed with phosphorus P and arsenic As in the active area regions which form the source lines 10, where they are needed to provide a gradual profile junction, specially adapted for erasing the memory cell.
The phosphorus implantation results in a well 9 being formed which accommodates a smaller well 8 in its interior, as shown in FIG. 2A.
P and As implants are also provided in the source regions or lines 10, where the field oxide 2 was present, shown in FIG. 2B. In these regions, the phosphorus and arsenic implantation wells are denoted by the numbers 7 and 14, respectively.
This is followed by a re-oxidation thermal treatment.
Subsequently, a dielectric layer, e.g., of TEOS, is deposited to evenly cover the whole structure. This dielectric layer is then etched back to define isolation spacers 12 which are laterally contiguous to each gate region 13.
This etching step is an anisotropic process conducted to simultaneously form the spacers 12 as well as openings 11 having a slight flare-out.
FIG. 1B shows the resultant structure, at the end of this TEOS back etching step and the start of an arsenic implantation step for both the source lines 10 and drain lines 17. This step is customarily referred to as the source and drain implantating step.
The processing steps described above are listed in sequential order herein below for convenience of illustration and of comparison to the inventive process to be described:
1) deposition of layers 3, 4, 5 and 6; PA1 2) 556 masking (bit lines); PA1 3) poly cap 6 etching; PA1 4) ONO etching; PA1 5) Poly1 etching; PA1 6) field oxide etching (self-aligned source and drain etching; PA1 7) removal of 556 mask; PA1 8) 585 masking (source implantation); PA1 9) P implant & As implant; PA1 10) re-oxidation thermal treatment of cell; PA1 11) TEOS deposition and etching; PA1 12) source and drain (S&D) arsenic implantation.
Turning back to the process step of implanting phosphorus and arsenic, it will be appreciated that the phosphorus implant diffuses more than the arsenic implant because of the thermal treatment. Accordingly, the effective length Leff of the cell will be the distance separating the well 9, formed in implanting the phosphorus on the source line 10 side, from the well 8, formed in implanting the arsenic on the drain line 17 side.
FIG. 2 is a schematic top view, drawn to an enlarged scale, of the layout of a semiconductor portion as subjected to conventional processing steps.
Shown in that Figure is a section line a-a' which lies parallel to the word lines of the cell matrix, in the active area zones unoccupied by field oxide.
FIG. 2A is a schematic, vertical section view of the semiconductor, shown in FIG. 2, taken along said line a-a'.
FIG. 2B is a schematic, vertical section view of the semiconductor, shown in FIG. 2, taken along a second line b-b' and highlighting regions where the field oxide is present.
From a comparison of FIGS. 2A and 2B, it can be appreciated that in the zone of the bit line 13 underlying the field oxide 2, the distance Lpar between wells 7 and 14, as respectively formed by a phosphorus implant and an arsenic implant, is equal to Leff. The distance Lpar is a mere parasitic distance between the wells 7 and 14, and the distance Leff is the spacing of the drain and source implant wells, both under the field and under the active area.
Electrical data from analyses of memory cell performance show that as the length Leff decreases, the number of the devices that fail increases due to a leakage current 15 flowing beneath the bit line between the source line 10 and the drain line 17.
These leakage current paths may occur both under the active area zone of the bit line (region F in FIG. 2) and under the zone underlying the field of the bit line (region G in FIG. 2).
Such a problem obviously imposes a dimensional constraint whereby the width of the bit line, and with it the overall dimensions of the memory device, cannot be reduced.